Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of complementary bit-lines), which is used for writing a bit into, or reading a bit from, the SRAM cell.
When integrated on system-on-chip (SOC) applications, the conventional 6T and 8T memories face the increasing demanding requirement of reducing power consumption and increasing speed. However, in conventional 6T memories, reduction in power consumption requires the operation voltage to be reduced. This results in a cell stability concern, which is caused by reduced Vcc_min, and hence reduced static noise margin (SNM).
In addition to the above-discussed problem, the SOC applications also face another dilemma. To reduce power consumption, when in a sleep mode or a low-power mode, the operation voltage of logic circuits can be reduced or turned off to save power. However, in SOC applications, the processor (central computing unit (CPU)) cannot be turned off, and it still needs to access level-1 (L1) cache memory. Since the operation voltage of the L1 cache cannot be lowered too much due to the required SNM, the operation voltage of the processor also cannot be reduced, and hence the reduction in overall power consumption is limited.